1. Field of the Invention
The present invention relates generally to methods for fabricating microelectronic fabrications. More particularly, the present invention relates to methods for fabricating gate electrodes within field effect devices within semiconductor integrated circuit microelectronic fabrications.
2. Description of the Related Art
Essential in the art of semiconductor integrated circuit microelectronic fabrication is the fabrication and use of field effect devices, such as field effect transistor (FET) devices. Field effect devices generally employ a gate electrode separated from a semiconductor substrate by a gate dielectric layer, to thus form a conductor/insulator/semiconductor capacitor, where charge carrier species concentrations are modulated within a channel region of the semiconductor substrate incident charge injection into the gate electrode.
While gate electrodes are thus desirable in the art of integrated circuit fabrication and often essential in the art of integrated circuit fabrication, gate electrodes are nonetheless not entirely without problems in the art of integrated circuit fabrication. In that regard, it is often difficult in the art of integrated circuit fabrication to fabricate gate electrodes with enhanced dimensional control and enhanced performance.
It is thus desirable in the art of integrated circuit fabrication to fabricate gate electrodes with enhanced dimensional control and enhanced performance.
It is towards the foregoing object that the present invention is directed.
Various gate electrode structures having desirable properties, and methods for fabrication thereof, have been disclosed in the art of integrated circuit fabrication.
Included among the gate electrode structures and methods for fabrication thereof, but not limited among the gate electrode structures and methods for fabrication thereof, are gate electrode structures and methods for fabrication thereof disclosed within: (1) Wu, in U.S. Pat. No. 5,710,454 (a stacked amorphous silicon layer method for forming a tungsten silicide polycide gate electrode); (2) Kimizuka, in U.S. Pat. No. 6,013,577 (an amorphizing ion implant method for forming a polysilicon gate electrode with an amorphous silicon surface; (3) Yu et al., in U.S. Pat. No. 6,162,716 (a multi-layer amorphous silicon gate electrode with mis-matched grain boundaries); and (4) Choi et al., in U.S. Pat. No. 6,188,104 (a trench field effect transistor (FET) device having formed therein a laminated amorphous silicon/polysilicon gate electrode). The disclosures of each of the foregoing references are incorporated herein fully by reference.
Desirable in the art of integrated circuit fabrication are additional methods and materials for forming, with enhanced dimensional control and enhanced performance, gate electrodes within integrated circuit devices.
It is towards the foregoing object that the present invention is directed.